Recording and reproducing method and apparatus for a digital audio signal and a reversed bit order digital video

ABSTRACT

A method can record or reproduce a digital audio signal and a digital video signal simultaneously. An N-bit (N: positive integer) digital audio signal is positioned at a higher bit side and an M-bit (M: positive integer) digital video signal is positioned at a lower bit side so as to form an (N+M)-bit digital signal which is recorded or reproduced in this condition. Since the digital video signal is positioned at the lower bit side, the digital video signal may not affect the reproduced audio signal even if the (N+M)-bit digital signal is processed as the digital audio signal in the reproducing process.

This is a continuation of application Ser. No. 07/533,583 filed Jun. 5,1990 and now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a method and an apparatus of recordingand reproducing both a digital audio signal and a digital video signalsimultaneously.

A current digital audio tape recorder (hereinafter refer to "DAT") isable to record and reproduce only an audio signal. However, it is veryconvenient to record and reproduce both the audio signal and anothersignal, such as a video signal of a static image, simultaneously.

In order to record and reproduce the video signal, for example, it canbe considered to record the audio signal on odd tracks and the videosignal on even tracks, i.e., to record each the signal on a signalchannel. In addition, it may be possible to record both the signals in aformat excluding the current audio format.

However, if the audio signal is recorded on one channel and the videosignal is recorded on the other channel in the audio format of the DAT,the video signal is reproduced as the audio signal when not using areproducing apparatus which can reproduce both the audio and videosignals. When the video signal is reproduced by the DAT only having anaudio signal reproducing apparatus function, the signal causes excessnoise and it is hard to use the DAT.

When both the audio and video signals are recorded in a format excludingthe current audio format, the current DAT cannot reproduce the audiosignal.

What is desired is a method and an apparatus which can record andreproduce both a digital audio signal and a digital video signalsimultaneously without having a bad influence on the audio signalreproducing operation of the current DAT.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, (N+M)-bit digitalsignal (N,M: positive integers) is formed by an N-bit digital audiosignal as higher bits and an M-bit digital video signal as lower bits.The digital signal is recorded and reproduced in a (N+M)-bits condition.

According to another aspect of the present invention, mixing means forms(N+M)-bit digital signal by mixing an N-bit digital audio signal ashigher bits and an M-bit digital video signal as lower bits. Recordingmeans records the (N+M)-bit digital signal from the mixing means on arecording medium.

According to a further aspect of the present invention, reproducingmeans reproduces (N+M)-bit digital signal from a recording medium, andthe recording medium stores the (N+M)-bit digital signal consisting ofan N-bit digital audio signal as higher bits and an M-bit digital videosignal as lower bits. Separation means separates the N-bit digital audiosignal and the M-bit digital video signal from the (N+M)-bit digitalsignal reproduced by the reproducing means.

According to an additional aspect of the present invention, a firstanalog-to-digital (hereinafter refer to "A/D") converter converts ananalog audio signal into an N-bit digital audio signal in response to afirst sampling clock. A second A/D converter converts an analog videosignal into an M-bit digital audio signal in response to a secondsampling clock. Timing conversion means converts a timing of the M-bitdigital video signal from the second analog-to-digital converter suchthat the digital video signal is synchronized with the first samplingclock. Mixing means forms an (N+M)-bit digital signal by mixing theN-bit digital audio signal from the first analog-to-digital converter ashigher bits and the M-bit digital video signal from the timingconversion means as lower bits.

According to another aspect of the subject invention, mixing means formsan (N+M)-bit recording digital signal by mixing an N-bit digital audiosignal as a higher bits and an M-bit digital video signal, where theN-bit digital audio signal is obtained by digitizing an analog audiosignal in response to a first sampling clock, and the M-bit digitalvideo signal is obtained by digitizing an analog video signal inresponse to a second sampling clock and processing through a timingconversion means. Separation means separates the N-bit digital audiosignal and the M-bit digital video signal from the reproduced (N+M)-bitdigital signal. The M-bit digital video signal from the separation meansis processed by the timing conversion means. The timing conversion meansincludes memory means having at least a pair of memories. An inputselection switch is provided at the input side of the memory means andis operated in an after-recording mode. The input selection switchreceives an input video signal and a reproduced video signal from thememory means. The reproduced video signal read from one memory of thememory means is written in another one of memory through the inputselection switch when the after-recording mode is selected. The videosignal read from the other memory and to be recorded is coincided withthe reproduced video signal read from the one memory.

According to an additional aspect of the present invention, mixing meansforms an (N+M)-bit recording digital signal by mixing an N-bit digitalaudio signal as a higher bits and an M-bit digital video signal, wherethe N-bit digital audio signal is obtained by digitizing an analog audiosignal in response to a first sampling clock, and the M-bit digitalvideo signal is obtained by digitizing an analog video signal inresponse to a second sampling clock and processing through a timingconversion means. Separation means separates the N-bit digital audiosignal and the M-bit digital video signal from the reproduced (N+M)-bitdigital signal. The M-bit digital video signal from the separation meansis processed by the timing conversion means. The timing conversion meansis constructed by memory means. In a recording operation, after thememory means acquires one scene of the M-bit digital video signal, astart code is added to the N-bit digital audio signal having relationwith the M-bit digital video signal, and both the digital signals areapplied to the mixing means. In a reproducing operation, after the startcode is detected from the N-bit digital audio signal from the separationmeans, the M-bit digital video signal having relation with the N-bitdigital audio signal is read from the memory means.

According to another aspect of the subject invention, mixing means formsan (N+M)-bit recording digital signal by mixing an N-bit digital audiosignal as a higher bits and an M-bit digital video signal, wherein theN-bit digital audio signal is obtained by digitizing an analog audiosignal in response to a first sampling clock, and the M-bit digitalvideo signal is obtained by digitizing an analog video signal inresponse to a second sampling clock and processing through a timingconversion means. Separation means separates the N-bit digital audiosignal and the M-bit digital video signal from the reproduced (N+M)-bitdigital signal. The M-bit digital video signal from the separation meansis processed by the timing conversion means. The timing conversion meansis constructed by memory means. The memory means is controlled for theM-bit digital video signal mixed first by the mixing means in connectionwith the N-bit digital audio signal such that a scene of at least theM-bit digital video signal is displayed in a line sequential manneruntil the memory means acquires one scene in a reproducing operation.

According to another aspect of a signal processing apparatus of thepresent invention, mixing means forms an (N+M)-bit recording digitalsignal by mixing an N-bit digital audio signal as a higher bits and anM-bit digital video signal, where the N-bit digital audio signal isobtained by digitizing an analog audio signal in response to a firstsampling clock, and the M-bit digital video signal is obtained bydigitizing an analog video signal in response to a second sampling clockand processing through a timing conversion means. Separation meansseparates the N-bit digital audio signal and the M-bit digital videosignal from the reproduced (N+M)-bit digital signal. The M-bit digitalvideo signal from the separation means is processed by the timingconversion means. The timing conversion means is constructed by memorymeans. A function switch is provided such that the memory means acquiresthe M-bit digital video signal in a desired timing manner during arecording operation. The memory means acquires the M-bit digital videosignal of a plural sequential scenes determined by the capacity of thememory means when the function switch is activated.

According to another aspect of the present invention, a signalprocessing apparatus of the subject invention, identification codeadding means adds a predetermined identification code to an M-bitdigital video signal. Mixing means forms an (N+M)-bit recording digitalsignal by mixing an N-bit digital audio signal as higher bits and theM-bit digital video signal as lower bits having the identification codeadded by the code adding means. Separation means separates the N-bitdigital audio signal and the M-bit digital video signal from thereproduced (N+M)-bit digital signal. Moreover, means is provided fordetecting the identification code from the M-bit digital video signalhaving the identification code from the separation means and forcontrolling to detect at least the M-bit digital video signal inaccordance with the identification code.

According to further aspect of the present invention, first bitinverting means inverts a desired bit of an M-bit digital video signal.Mixing means forms an (N+M)-bit recording digital signal by mixing anN-bit digital audio signal as higher bits and the M-bit digital videosignal from the first bit inverting means as lower bits. Separationmeans separates the N-bit digital audio signal and the M-bit digitalvideo signal from the reproduced (N+M)-bit digital signal. Second bitinverting means inverts again the bit of the M-bit digital video signalfrom the separation means, where the bit is inverted by the first bitinverting means.

According to another aspect of the present invention, mixing means formsan (N+M)-bit recording digital signal by mixing an N-bit digital audiosignal as higher bits and an M-bit digital video signal as lower bits.Separation means separates the N-bit digital audio signal and the M-bitdigital video signal from the reproduced (N+M)-bit digital signal. Acharacter generator generates a video signal of an image to besuperimposed. Means is provided for inserting the video signal from thecharacter generator into the reproduced video signal from the separationmeans. A predetermined image can be superimposed on the scene of thereproduced video signal.

Thus, both the digital audio signal and the digital video signal can berecorded and reproduced simultaneously. Since the digital video signalis positioned at the lower bit side, the digital audio signal can bereproduced without receiving an influence from the digital video signalwhen reproducing the (N+M)-bit digital signal as the digital audiosignal.

The objects, advantages and novel features of the present invention willbe apparent from the following detailed description when read inconjunction with the appended claims and attached drawing.

BRIEF DESCRIPTION OF DRAWING

FIGS. 1A and 1B show a block diagram of one embodiment of a signalprocessing apparatus according to the present invention;

FIGS. 2A-D show one example of digital signal formats;

FIGS. 3 through 6 show identification codes;

FIG. 7 shows a bit inverting process of a digital video signal;

FIGS. 8A-G show a time chart for explaining a postrecording process;

FIGS. 9 and 10A-E show time charts for explaining an operation of amonitor;

FIG. 11 shows a flow chart of accomplishing a continuous display mode;

FIG. 12 shows a time chart of the continuous display mode;

FIG. 13 shows a block diagram of one example of a current DAT;

FIG. 14 shows a waveform of a video signal;

FIGS. 15 through 18 show frequency spectrum diagrams of a reproducedvideo signal;

FIGS. 19A and 19B show a block diagram of another embodiment of thesignal processing apparatus according to the present invention;

FIGS. 20A-B and 21 show a process of a superimposing operation;

FIGS. 22A and 22B show a block diagram of a further embodiment of thesignal processing apparatus according to the present invention; and

FIGS. 23 through 26A-F show time charts explaining a line sequencedisplay operation.

DETAILED DESCRIPTION OF THE INVENTION

Preferred embodiments of the present invention will be discussed byreference to the attached drawings.

Referring now to FIGS. 2A-D, a format (bit organization) of a digitalsignal DS is shown where the digital signal consists of a mixture of anaudio signal Sa and a video signal Sv. In this embodiment, NTSC videosignal is used, but PAL, SECAM or the like can be used as the videosignal similarly to NTSC.

This present invention uses a standard bit number of the digital signalDS of the DAT shown in FIG. 2C by considering a compatibility with aconventional system and a quality of the reproduced audio signal. Thedigital signal DS is divided into two groups as shown in FIGS. 2A and2B, wherein the higher bit side thereof is assigned to a digital audiosignal DSa and the lower bit side thereof is assigned to a digital videosignal DSv.

In the audio format standard, assuming that T (positive integer) is atotal bit number, N (positive integer) is a bit number of the digitalaudio signal DSa and the remainder M (=T-N) is a bit number of thedigital video signal DSv, a good result may be obtained by selecting asfollows when T=16:

    N>=1/2T

A useful condition in this situation is N=8 through 10. Thus, thedigital video signal DSv may consist of 6 through 8 bits. In thisembodiment, N=10 and M=6 as shown in FIGS. 2A and 2B.

The digital audio signal DSa and the digital video signal DSv are mixedsuch as the digital audio signal DSa is positioned at the higher bitside. Thus, the higher ten bits are assigned to an area of the digitalaudio signal DSa and the lower six bits are assigned to an area of thedigital video signal DSv (FIG. 2C).

If a measure is taken to meet the noise situation of the audio signalSa, e.g., a noise reduction process is applied to the audio signal Sa,before mixing with the video signal Sv, the relationship of these signalmay not be determined by reference to the above expression. In otherwords, the bit number of the audio signal Sa may be reduced.

The digital signal DS of such a bit format is applied to a rotarymagnetic head of the DAT (not shown) in order to record on and reproducefrom a magnetic tape.

As described hereinafter, the DAT records both left (L) and right (R)channels of the digital audio signal DSa in sequence, where the left andright channels are sampled in response to a sampling clock fs. Thesampled data of the digital video signal DSv is processed to be mixedwith the digital audio signal DSa in synchronism with a clock 2 fs inorder to be recorded.

Assuming that the frequency of the audio sampling clock fs is 48 KHz andthat of the video sampling clock is 3 fsc (fsc=3.58 MHz), a frequencyratio of the video sampling clock 3 fsc to the clock 2 fs is 112. Thus,the digital video signal is sampled every period 1/3 fsc and the sampleddata is recorded in sequence every period 1/2 fs (=112 * 1/2 fs).

Since one field period is 1/60 seconds, it takes about 1.87 (=1/60 *112) seconds to record one field video signal. However, anidentification code ID is added to the video signal as discussedhereinafter, so that a total recording time of one field video signalmay be about 2 seconds.

The period of the audio signal (narration or BGM) corresponding to theimage contents of the video signal may be over 2 seconds in general, sothat the applied audio for one scene of the image may be recorded forover 2 seconds.

As a result, a plurality of image scenes (or pictures) may be inserteduntil the audio signal is completed if the audio signal is timereferenced.

Taking into consideration a search process, it may be better to add adesired identification code to the video signal (image data) and mixsuch a video signal with the audio signal. The signal format isdetermined by reference to such a condition.

FIG. 3 shows one example of such a format. The identification code ID isadded before and after the video signal (image data) to be inserted intothe audio signal (audio data). In this example, the identification codeID consists of a start code section SID added just before the videosignal and a stop code section EID added just after the video signal.

The start code section SID is used for the following objects.

(1) the identification code only for the video signal data or the imagedata;

(2) the identification code for explaining the video signalorganization, namely, indicating whether the video signal is a compositevideo signal, a combination of a luminance (V) signal and a color (C)signal, or a component signal of red (R), green (G) and blue (B);

(3) indicating a quantization bit number of the image data; and

(4) location search code (LSID) for the image data.

These objects are only examples. In order to accomplish these usageobjects, the start code section SID would be organized as follows.

FIG. 4 shows an example of such a organization. As shown in this figure,the start code is a six-bit code in which only the least significant bit(LSB) is "1". Similarly, the stop code EID is a code of all "0".

One block consists of six bits, and the start code section SID consistsof (4800+1) blocks (about 50 msec). A main block consists of 600 blocksof the start code section, and the same code data are inserted into eachthe main block. Thus, the start code section SID can be searchedregardless of a reproducing start position.

The main block is divided into 20 sub-blocks each having 30 blocks. Thefirst 12 blocks F0-F11 of the sub-block are used for framing codes. Whenall the blocks of the sub-block are the start codes and "0" is assignedto them, the sub-blocks F0-F11 of "0" are identified as the framingcode.

The other eight sub-blocks D0-D7 are used as mode codes. One example ofthe mode code is shown in FIGS. 5A-B, and the contents thereof are onlyexample.

In this example, the stop code section EID consists of eight blocks(about 83 micro seconds) as shown in FIG. 4. A predetermined blankingperiod is assigned to the latter half of the stop code section EID. Anunit area (about 2 seconds) of one image data is from the head of thestart code section SID to the end of the blanking period. This unit areaperiod corresponds to 120 times longer than the vertical period.

Since one phase cycle of the subcarrier fsc is four fields, it ispossible to avoid a discontinuity of the subcarrier fsc for the staticimage video signal Sv recorded continuously by setting the unit area asan integer multiple of four times longer than the vertical period, e.g.,as 120 times longer than the vertical period.

FIGS. 1A-B show one embodiment of a signal processing apparatus whichprocesses the digital signal DS as discussed hereinbefore, records it onthe DAT, and separates the reproduced digital signal DS into theoriginal audio signal Sa and the original video signal Sv.

A signal process system for the audio signal Sa will be described. Theaudio signal Sa applied at an audio input terminal 12 is applied throughan amplifier 14 to a low pass filter (LPF) 16 so that the bandwidth ofthe signal is limited. The output signal from the low pass filter isconverted into the ten-bit digital audio signal DSa by an A/D converter18. The audio sampling clock for this digitizing operation is fs (48KHz).

The digital audio signal DSa is applied to mixing means (adder) 20 ofmixing/separation means 86 in order to mix with the digital video signalDSv which will be described hereinafter.

The result digital signal DS (FIG. 2C) is applied to a digital outputprocessing circuit 22 for converting it into a digital signal having astandard audio format.

As is well known, the digital output processing circuit 22 includesclock generation means for producing a bit clock BCK. The formatteddigital signal DS is applied through a terminal 24 to a rotary magnetichead in order to record it.

The digital signal reproduced by the rotary magnetic head is applied viaa terminal 32 to a digital processing circuit 34 which processes it forthe digital input. For example, a phase lock loop (PLL) circuit (notshown) is activated to produce a reproducing bit clock BCK insynchronism with a master clock.

A separation signal is produced in accordance with the master clock toseparate the digital signal into the digital audio signal DSa and thedigital video signal DSv. Thus, the next stage, separation means 36,generates the separated digital audio signal DSa and the separateddigital video signal DSv (FIGS. 2A and 2B).

A digital-to-analog (D/A) converter 38 converts the separated ten-bitdigital audio signal DSa into an analog signal whose bandwidth islimited by a low pass filter 40. The output signal from the low passfilter 40 is applied through an amplifier 42 to an audio output terminal44.

The signal processing system of the video signal will be discussedhereinafter. The video signal Sv of the static image at an video inputterminal 50 is applied via an amplifier 52 to an A/D converter 54 whichconverts it into a six-bit digital video signal DSv. The frequency ofthe sampling clock for this conversion is an integer multiple of thesubcarrier fsc, e.g., 3fsc in this embodiment.

The digital video signal DSv is applied to memory means 60 via aselection switch 56 for selecting the input signal or the reproducedsignal and another selection switch 58 for postrecording.

The memory means 60 operates as timing converting means for the digitalvideo signal DSv. In other words, the memory means 60 is used to expandthe timing of the digital video signal DSv when reading it insynchronism with the bit clock BCK in order to combine the digital videosignal DSv with the digital audio signal DSa, and the memory means 60 isused to reduce the timing the reproduced digital video signal DSv.

The memory means 60 includes a pair of memories 62 and 64 and associatedmemory control (CTL) circuits 70 and 72. The digital video signal DSv isstored in the memory 62 or 64 alternately every field under control ofthe memory control circuits 70 and 72.

In a case that only a single scene or picture is inserted in a singleshot mode, one-field video signal is stored in one the memories. In acase that the same scene is inserted continuously, the stored videosignal is read repeatedly. In a case that different scenes are insertedcontinuously, the video signal is acquired at intervals of apredetermined period and stored in the memory 62 or 64 alternately.Since it takes about two seconds to read the data from the memory 62 or64, the predetermined period should be over two seconds.

The writing clock of the memories 62 and 64 is 3fsc and the readingclock thereof is 2fs in order to match the timing of the digital videosignal DSv against that of the digital audio signal DSa with keeping thesynchronization.

A reference number 100 represents control (CTL) means for the memoriesor the like which receives the subcarrier fsc extracted by a subcarrierextraction circuit 110. The control means 100 applies a control signalto the memory control circuits 70 and 72 in response to the subcarrierfsc.

A switch 124 controls the recording mode or the reproducing mode of thesignal processing apparatus 10, and the mode is determined by referenceto the selection condition of this switch. A switch 126 is a codeinsertion switch which is used to insert the start code SC for the audiosignal into the sub-code of the DAT. However, this operation will bediscussed in detail hereinafter.

The control means 100 receives the bit clocks BCK from the digitaloutput processing circuit 22 and the digital input processing circuit34. Thus, the control means 100 applies control signals to the memorycontrol circuits 70 and 72 so as to generate readout clocks RCK (=2fs)in synchronism with the bit clock BCK.

As a result, both the digital audio signal DSa and the digital videosignal DSv are applied to the mixing means 20 in synchronism with thebit clock BCK.

The digital output processing circuit 22 produces a bit switch signal BSfor switching between the 10-bit mode and the 6-bit mode in response tothe bit clock BCK, but the detail operation will not be discussed. Themixing means 20 receives the bit switch signal BS and mixes the 10-bitdigital audio signal DSa and the 6-bit digital video signal DSv as shownin FIG. 2C.

A reference number 112 represents a vertical synchronization (sync)signal separation circuit which extracts or separates the vertical syncsignal from the digital video signal DSv and applies it to the controlmeans 100. As a result, each of the memories 62 and 64 can store onefield of the digital video signal DSv by reference to the vertical syncsignal.

A pair of output selection ganged switches 66 and 68 are provided at thenext stage of the memories 62 and 64. The output selection switch 68 isused for the signal recording period, and the other output selectionswitch 66 is used for the signal reproducing period.

The digital video signal DSv read alternately from the memories 62 and64 by the output selection switch 68 is applied to a sync bit shiftencoder 76 which process to shift the sync bit.

Since the video signal is converted into the six-bit data by the A/Dconverter, it is general that the sync bit is a digital data of all "0".However, only the sync bit is processed to be bit shifted because theidentification code ID is applied to the bit which has no relation tothe image as shown in FIG. 6 by considering the above discussedidentification code ID. Thus, it is possible to distinguish theidentification code ID from the sync bit.

In the recording operation, the sync bit is shifted by one bit and theidentification code ID is added by an adder 78. A reference number 80represents a generator for the identification code ID.

A signal processing circuit 82 acts as a parallel-to-serial (PS)converter for the digital video signal DSv having the identificationcode ID. Moreover, in this circuit 82, the most significant bit (MSB) ofthe digital video signal DSv is bit inverted. This process will bediscussed hereinafter.

After completing the predetermined signal processing operation for thedigital video signal DSv, a format conversion circuit 84 converts theformat of this digital video signal into the format satisfying the DATstandard. The output signal from the format conversion circuit 84 ismixed with the digital audio signal DSa as shown in FIG. 2C and themixed signal is transferred to the DAT.

When reproducing the digital signal DS, the separation means 36separates the digital audio signal DSa and the digital video signal DSv.The format of the separated digital video signal DSv is converted intothe original format by a format inversion circuit 88. A signalprocessing circuit 90 executes the serial-to-parallel (SP) conversionfor the output signal from the format inversion circuit 88 and invertsthe MSB of the digital video signal DSv again.

After that, a sync bit shift decoder 92 shifts the output signal fromthe signal processing circuit 90 reversely with respect to the sync bitrecording operation in order to obtain the original sync bit (see FIG.6).

The digital video signal DSv from the sync bit shift decoder 92 isapplied to the memories 62 and 64 via the selection switches 56 and 58.Thus, the reproduced digital video signal DSv is written in thesememories in response to the writing clock WCK (=2fs) synchronized withthe bit clock BCK. The memories are read in response to a readout clockRCK (=3fsc) having relation to the subcarrier fsc.

The digital video signal DSv from the output selection switch 66 isapplied via an input/output monitor selection switch 102 to a D/Aconverter 104 which converts its input into an analog signal. Theconverted signal is applied through an amplifier 106 to a video outputterminal 108. Monitor means (not shown) is provided at the video outputside.

Identification code detection means 94 is provided at the output side ofthe signal processing circuit 90 to detect the identification code ID,and the detected identification code ID is applied to the control means100. This identification code ID is used to control the memory controlcircuits 70 and 72, and the signal processing operation is modified byreference to the mode information.

When the digital video signal DSv having the identification code ID isreproduced and stored in the memory means 60, only image data is stored.In this instance, the final image data appears when a predetermined timehas passed from the initial data of the image data. In order to detectaccurately the final image data, time management is done and the stopcode section EID is detected. It may be desirable that the final imagedata is determined when the time management result matches the stop codedetection. After completion of storing the final image data, theoperation modes of the memories 62 and 64 are changed from the writingmode to the readout mode and the output selections of the switches 66and 68 are changed.

If the reproducing mode of the DAT stops during the reproducing periodof the digital video signal DSv, the reproduced output data at theterminal 32 is all "0" as shown in FIG. 7. Since the time management(counting-up operation) for the image data is executed in the signalprocessing apparatus 10, the counting-up operation will be continuedeven if the DAT changed to the stop mode.

Thus, the memory means 60 is kept in the writing mode, so that the dataof all "0" may be stored as the image data in the memory, e.g., thememory 64.

After a predetermined time has passed from the stop mode, it is thereproducing time for the final image data. In this instance, thereproduced data is all "0", so that this data is judged by mistake asthe stop code section EID. The signal processing apparatus 10 regardsthat the final image data is applied, and instructs the memory means 60to change from the writing mode to the readout mode and the selectionswitches 66 and 68 to change the their selection. Thus, the memory 64 iscontrolled to the readout mode.

The data "0" stored in the memory 64 after the stop mode of the DAT isread and monitored as the image. The image of the data "0" is blackdisplay, and an improper image may be monitored.

In order to avoid this effect, the MSB of the image data is inverted andrecorded and the reproduced MSB is inverted again. Thus, the result MSBis "1" as shown in FIG. 7 even if the reproduced output of the stop modeis all "0".

Thus, the signal processing apparatus 10 has the following advantages.

(1) avoiding to misjudge the data as the final image data; and

(2) avoiding to control to change the operation mode of the memory means60.

The previous scene is monitored always because of the advantage (2), sothat the above discussed disadvantage is improved.

As shown in FIG. 1A, at least two function switches 120 and 122 areprovided at the signal processing apparatus 10. One of these switches isa mode switch and the other one is a shutter switch. The mode switch 120is used to select whether the scene to be inserted is a single shotscene or a sequential scene. The shutter switch 122 is used to selectthe desired scene to be inserted when the inserted scene is in thesingle shot mode.

The postrecording operation will be discussed hereinafter. Whenpostrecording the audio signal, the inserted image is not changed. TheDAT is changed in the reproducing mode and the screen is monitored. Whenthe scene corresponding to the postrecording is displayed, thepostrecording mode is selected. The memories 62 and 64 are switchedalternately between the writing and reading modes. However, theoperation mode of the memory is fixed while postrecording the audiosignal.

For example, when the postrecording mode is selected while monitoringthe image data of the memory 62, the image data of the memory 62 isalways monitored and the image data of the memory 64 can be recorded inthe DAT.

The image data of the memory 62 is not equal to that of the memory 64 ingeneral. Since an operator does the postrecording operation by watchingthe monitor screen, the scene of the monitor would be different from thescene to be recorded by the postrecording operation.

In order to avoid this phenomenon, the scene to be monitored should bethe scene to be recorded in the postrecording mode. For this end, theselection switch 58 for the postrecording is provided in a hardware.

The postrecording mode will be described by reference to FIGS. 8A-G. Itis assumed that the selection switches 66 and 68 are in the conditionshown in FIGS. 1A-B (see FIG. 8F).

A write enable signal/WE is outputted not to store the identificationcode ID added to the digital video signal DSv (FIGS. 8A and 8C). Whenthe location search code LSID of the identification code ID is detected,an address clear pulse will be output (FIG. 8B). When the shutter switch122 is pushed while the memory 64 is in the writing mode (FIG. 8D), thecontrol means 100 judges the postrecording mode and fixes the operationmode of the memory means 60 to the previous operation mode.

The frequency of the writing clock RCK for the memory 64 is changed from2fs to 3fsc immediately after the postrecording switch 58 is changed tothe terminal C of FIG. 1A (FIG. 8E). Then, the image data of the memory62 is applied to the memory 64 via the postrecording switch 58. Thus, ahigh speed rewriting operation may be realized. Therefore, the imagedata of the memory 62 may be equal to that of the memory 64, and themonitor scene may be equal to the image data to be recorded.

After completing the writing operation, the write enable signal/WE forthe memory 64 is inverted and the image cannot be written. Thepostrecording switch 58 may return to the original positionautomatically, i.e., the switch may be changed to the terminal d (FIG.8G). For releasing the postrecording mode, the shutter switch 122 ispushed during the reproducing mode or the mode switch 120 issequentially changed.

It takes about two seconds to store the video signal of one scene in thememory means 60. For example, when reproducing the digital signal DS inwhich one scene 1 is inserted for one audio signal (e.g., audio 1) asshown in FIG. 9, there may be no image on the monitor screen until thevideo signal of the initial scene (scene 1) is completely stored in thememory means 60 (about 2 seconds). After the video signal of the initialscene 1 is completely stored, the scene may be monitored on the screen.However, the audio is already reproduced. As a result, timings of themonitored scene and the audio are lagged by 2 seconds at the initialperiod.

In order to avoid this phenomenon, the insertion timing of the videosignal should be shifted previously by a predetermined time. For thisend, as shown in FIG. 10A, the video signal (scene 1) corresponding tothe audio signal (audio 1) is previously acquired before the audiosignal is recorded. The video signal is acquired by controlling theshutter switch 122 (FIG. 10B).

After a predetermined period has passed from the acquisition of thevideo signal, the start code SC of the DAT sub-code (FIG. 10C) is inputso as to acquire the audio signal. The start code SC is input by thecode insertion switch 126 as shown in FIG. 1A.

When the code insertion switch 126 is activated, the control means 100applies an instruction to the digital output processing circuit 22 andthe start code SC based on the DAT format is inserted into the digitalaudio signal DSa. Then, the digital audio signal DSa is applied to themixing means 20 in synchronism with the insertion of the start code SC.

The predetermined period is determined by the period while thereproduced digital video signal DSv is stored in the memory means 60(about two seconds).

The digital video signal DSv is stored in the memory means 60 for thereproducing period. When the start code SC is detected after the digitalvideo signal DSv of one scene is stored, the control means 100 transfersthe selection control signal to the memory means 60, the selection ofthe switches 66 and 68 are changed in synchronism with the start code SCand the memory means 60 becomes in the readout condition (FIG. 10D).

As a result, the readout operation of the memories 62 and 64 issynchronized with the audio signal, so that the scene would not appearon the monitor with being delayed from the audio (FIG. 10E).

The sequence mode of the video signal will be discussed. As describedhereinbefore, when the mode switch 120 is changed to the sequentialside, the video signal at the terminal 50 is acquired automatically inthe memory means 60 at intervals of about 2 seconds. On the other hand,the video signal of one field is acquired every time when the shutterswitch 122 is pushed while the mode switch 120 is changed to the singleside. The acquisition interval should be at least two seconds because ittakes about two seconds to read the data from the memory means 60.

In a case that the scene is inserted into the audio signal in real time,it is desirable to acquire the scene in sequence. It is necessary toacquire some sequential scenes especially for the moving image. However,the sequential mode may be impossible if the acquisition timing of thevideo signal is set by considering the data readout period of the memorymeans 60.

Thus, the sequential mode is added to acquire the sequential scenes. Anumber of scenes acquired in sequence depends on a number of thememories. Since this embodiment employs two memories 62 and 64, themaximum number of scenes to be acquired is two within the period whilethe video signal of one scene is recorded, i.e., within the readoutperiod of the memories 62 and 64 (about two seconds in this embodimentas discussed hereinbefore).

FIG. 11 shows a flow chart of one example of the sequential mode controlprogram for a central processing unit (CPU) of the control means 100,and this program will be discussed by reference to FIG. 12.

A count value n of a counter is set to an initial value 1 (step 232),and the single mode is checked (step 234). If the single mode is notselected, the CPU checks the transmission condition of the image data ofone scene (data readout condition of the memories 62 and 64) (step 236).If the image data is completely transferred, the video signal of thenext scene is automatically written in the memory means 60 (step 238).This is the described sequential mode.

In the single mode, the contents of the counter is checked (step 240).If the counter value is the initial value (=1), the operation conditionof the shutter switch 122 is checked (step 242). When the shutter switch122 is pushed, the counter is incremented (=2) (step 244). Then, thememory means 60 stores the video signal when the shutter switch 122 ispushed (step 246).

As shown in (1) of FIG. 12, the counter is reset to the initial valueand returns to the standby condition after completing the transfer ofthe image data of the one scene (steps 248, 250 and 234). It takes 1/60seconds to acquire the video signal of one scene.

In the single mode, when the shutter switch 122 is activated repeatedly,the counter value keeps "2" as shown in (II) of FIG. 12 before the imagedata of one scene is completed to be transferred at that timing. Thus,this situation is passed through the steps 240 and 252 to a step 254,where the operation condition of the shutter switch 122 is checked.

When the second operation is detected, the counter is incremented (=3)(step 255). Then, the memory means 60 stores the scene of the videosignal at the second operation of the shutter switch (step 256). Whenthe second transmission of the video signal is completed, the apparatusis in the standby condition after the counter is reset to the initialvalue (steps 258 and 260).

When the shutter switch 122 is operated for acquiring the third sceneduring the transmission period of the image data for the second sceneafter the second scene is acquired, the video signal may not be acquiredbecause this operation timing is in the period while the video signal isrecorded (see (III) of FIG. 12).

While the second scene is acquired, the counter value remains at "3"because the counter is not reset to the initial value as understood fromthe steps 258 and 260. When the shutter switch 122 is pushed in thissituation, the counter value is checked in step 252. Since the processadvances directly to step 258 if the counter value is not "2", the thirdscene may not be acquired.

Thus, even if the shutter switch 122 is activated twice or over twicewithin two seconds, only the initial two scenes may be acquired. Byrecording the scenes in this sequential mode, each scene can bemonitored for two seconds in the reproducing mode.

According to this invention constructed as discussed hereinbefore, boththe audio signal Sa and the video signal Sv can be mixed in the currentaudio format. In this instance, the quantization bit number of the audiosignal Sa is decreased from 16-bit organization to 10-bit organizationwithout having a bad influence on the audio signal. Moreover, 6-bitquantization may be enough for the video signal because it is a staticimage.

Even if a current DAT reproduces the digital signal DS including theaudio signal Sa and the video signal Sv, i.e., even if the digital videosignal DSv is reproduced as the digital audio signal DSa by a DAT notincluding the video reproduction system as shown in FIG. 13, the audiosignal may not receive bad influence.

In this instance, the video signal Sv may be a noise component for theaudio signal Sa. However, a dynamic range of the audio signal Sa may beabout 6 Ndb, because the digital video signal DSv is inserted as thelower bits with respect to the digital audio signal DSa as shown in FIG.2C.

By selecting about 10 bits as the quantization number N, the dynamicrange may satisfy the level of the compact cassette or Dolby B(trademark). Thus, when the video signal is reproduced simultaneouslywith reproducing the audio signal, the audio signal Sa may not receive asubstantially bad influence from the video signal.

If the bit coupling position is modified such that the LSB data V0 ofthe digital video signal DSv is positioned at the side of the LSB dataA0 of the digital audio signal DSa as shown in FIG. 2D, the audio signalSa may not receive substantially completely bad influence.

This reason will be discussed hereinafter. When the digital video signalDSv is added to the lower bit side of the digital audio signal DSa, theMSB bit data V5 of the digital video signal DSv is positioned at the MSBof the video area and the LSB data V0 thereof is positioned at the LSBof the video area in normal as shown in FIGS. 2B and 2C.

When the video signal Sv is digitized, as shown in FIG. 14, the MSB(=V5) may be "1" for the luminance level higher than the centerluminance level (dotted line) as a reference level and the MSB may be"0" for the luminance level lower than the reference level.

The video signal Sv is a cyclic signal repeated every horizontal period.One horizontal period is about 63.5 micro seconds. Since the timing ofthe video signal is expanded by 112 times for the recording andreproducing operations, the reproduction frequency may be about 140 Hz(1/(63.5 micro seconds * 112)=140 Hz).

FIG. 15 illustrates a spectrum diagram of the reproduced frequency wherenoise peak appears every about 130 Hz. FIG. 16 illustrates a spectrumdiagram in which a frequency range is expanded to 20 KHz.

In the reproducing operation, about -60 dB of the reproduced frequencylevel is inserted as noise to the reproduced audio signal Sa. Thus, alistener may sense slightly the reproduced video signal as noise.

On the other hand, according to this invention, the digital video signalDSv is added to the digital audio signal DSa by changing the bit weightof the video signal as discussed hereinbefore. In other words, if theMSB data V5 is positioned at the LSB and the LSB data V0 is positionedat the MSB, the reproduced level of the MSB data V5 is very small anddoes not affect the reproduced audio.

Since the LSB data V0 varies frequently within one horizontal period,the reproduced frequency of the reproduced LSB data V0 is very high.Thus, it appears as white noise.

However, the reproduced frequency is very high and the reproduced outputlevel is very small, so that this component does not affect the totaloutput. Thus, noise in the reproduced audio signal Sa can be reducedvery much by comparison with the organization of FIG. 2C.

FIGS. 17 and 18 illustrate the reproduced frequency spectrum diagrams inwhich the video data is organized as shown in FIG. 2C. These FIGS. 17and 18 correspond to FIGS. 15 and 16, respectively.

FIGS. 19A and 19B show another embodiment of the signal processingapparatus according to this invention. This embodiment has a function tosuperimpose a special image on a static scene. In FIGS. 19A-B, the sameelements as FIGS. 1A-B are represented by the same reference numbers andthe detailed description thereof will not discussed.

In this embodiment, the digital video signal DSv whose bits areprocessed by the sync bit shift encoder 76 is applied to the adder 78via a selection switch 140 which is used for inserting the imageinformation (code data) for the superimposing operation. The switch 140is controlled by the control means 100.

A character generator 136 is used for superimposing a predeterminedimage on the monitor screen. A CPU 134 controls the operation of thecharacter generator 136. The CPU is connected to a keyboard 142 forreceiving the superimposing image information, such as the timing thekind of scene and the period of the image to be superimposed.

A sync signal generation circuit 138 receives the reproduced videosignal from the D/A converter 104 via a line C. Then, the sync signalgeneration circuit 138 generates the horizontal and vertical syncsignals in synchronism with the reproduced video signal, and these syncsignals are applied to the character generator 136. Thus, thesuperimposed image is synchronized with the monitor screen.

The video signal of the image to be superimposed is applied from thecharacter generator 136 to an adder 132 provided between the D/Aconverter 104 and the amplifier 106, and this video signal is mixed withthe reproduced video signal. The character generator 136 may be, forexample, a read only memory (ROM) storing a predetermined image.

This embodiment is constructed as described hereinbefore, and the otherportions are the same as FIGS. 1A-B. The operation of this embodiment isthe same as FIGS. 1A-B except the superimposing mode which will bediscussed hereinafter.

The superimposing mode is a special mode in which a special image Y isinserted or added to the monitor image X. The representative examplesare shown in FIGS. 20A and 20B.

In order to accomplish such a special mode, the following process andoperation may be done. The superimposing mode needs at least information(image information) regarding the monitor image, the image to besuperimposed, the screen area and the insertion period. For this end,the image information (superimposing data) should be inserted instead ofthe video signal into the audio signal as shown in FIG. 21. Theinsertion data would be input through the keyboard 142.

While the image data is inserted, the selection switch 140 is in thecondition shown by the doted line. This switching operation isinstructed by the control means 100.

In the reproducing operation, when the image information is inserted, acode indicating such a situation is inserted into the start code sectionSID of the identification code ID in this embodiment in order to usethis image information only for the superimposing operation. Thisexample is shown in FIG. 5B.

When the superimposing mode is detected from the start code section SIDin the reproducing operation, the control means 100 transmits a controlsignal via a line a to the CPU 134 such that the CPU 134 acquires thenext data. The image data is acquired through a line b.

Even if the stop code section EID inserted at the end portion of theimage information is detected at this process, the memory means 60 iscontrolled such that the selection switches 66 and 68 are not changed.Thus, the video signal of the scene 1 is continuously read as shown inFIG. 21 for the period that the image information is inserted.Therefore, the same scene as the previous scene is continuouslymonitored for this period.

Since a special identification code ID is not added to the image data 2inserted after the image information, the monitor screen is changed tothe scene 2 when the stop code section EID is detected. Then, thespecial image specified by the image information is read from thecharacter generator 136, and it is superimposed on a predeterminedposition of the monitor scene 2 for the predetermined period. After thepredetermined period has passed, the normal monitor operation may berecovered. The CPU 134 manages the position of the inserted image, theinsertion position, the predetermined period or the like.

FIGS. 22A and 22B illustrate an additional embodiment of the signalprocessing apparatus 10 according to this invention.

In the above discussed embodiment, the insertion timing of the videosignal is previously lagged by the predetermined time in order to avoidthat the initial monitor image is delayed with respect to the audio.However, in this embodiment, the monitor image is displayed in a linesequence. In this FIGS. 22A-B, the same elements as FIGS. 1A-B arerepresented by the same reference numbers, and the detailed descriptionwill be eliminated.

In this embodiment, buffer memory means 130 receives the digital videosignal DSv whose sync bit is shifted reversely with respect to therecording operation by the sync bit shift decoder 92. The buffer memorymeans 130 includes a pair of line memories, e.g., 2H line memories 132and 134 in this embodiment. The reproduced video signal DSv is writtenin and read from the memories 132 and 134 alternately every 2H. Anobject to provide the buffer memory means 130 is that the line sequencedisplay mode is accomplished when monitoring the initial scene, and itwill be described in detail.

The digital video signal DSv from the buffer memory means 130 is appliedto the memories 62 and 64 via the selective switches 56 and 58. Thereproduced digital video signal DSv is written in response to thewriting clock WCK (=2 fs) synchronized with the bit clock BCK, and it isread in response to the reading clock RCK (=3 fsc) having relation tothe subcarrier.

This embodiment is constructed as described, and the other portion isthe same as FIGS. 1A-B. The operation of this embodiment is the same asthat of FIGS. 1A-B except the line sequence display which will bediscussed hereinafter.

As discussed hereinbefore, it takes about two seconds to store the videosignal of one scene in the memory means 60. In a case that the digitalsignal DS is reproduced where the same scene is inserted to the singleaudio signal (e.g., audio 1) many times as shown in FIG. 23, no image isdisplayed on the monitor until the video signal of the first scene(scene 1) is stored in the memory means 60. After all the video signalof one field for the first scene 1 is stored, this scene may bemonitored. After that, the same video signal is used repeatedly. Thus,the monitor is displayed as shown in FIG. 23.

However, it is desirable to monitor the first scene 1 in synchronismwith the reproducing operation of the audio signal. It takes at leastabout two seconds to store the video signal of one scene in the memorymeans 60, because the audio sampling clock fs is used as the writingclock.

For improving this disadvantage, the first scene is displayed on themonitor in the line sequence manner as shown in FIG. 24. Thus, the firstscene can be monitored in synchronism with the audio signal. The linesequence display mode is applied only to the period while the firstscene is stored in the memory means 60, and the stored video signal isused later for the scene sequence display.

The line sequence display mode is applied when the contents of the sceneare changed. If a plurality of scenes are inserted into a single audio,the monitor display is done as shown in FIG. 25.

For accomplishing the above discussed operation, the buffer memory means130 are provided as shown in FIGS. 22A-B. The reproduced digital videosignal DSv is written in the pair of line memories 132 and 134alternately as shown in FIGS. 26A and 26B in response to the audiosampling clock fs. The stored video signal is read alternately from theline memories 132 and 134 in response to the video sampling clock 3 fsc.The reading timing is synchronized with the vertical blanking pulse VBLK(FIG. 26C). In this embodiment, the readout operation is done insynchronism with the vertical blanking pulse VBLK obtained just afterthe writing operation.

After that, the memory 62 (or 64) writes the data again. Thus, the videosignal is written in the memory 62 every 2H in sequence by using thevideo sampling clock 3 fsc. After completing the writing operation, thereadout mode is applied. While the next 2H video signal is writtenagain, all the written video signal is read by using the video samplingclock 3 fsc. This read video signal is monitored (FIGS. 26D through26F).

Therefore, the first 2H video signal is read and monitored. In the nextreading mode, the first rewritten 2H video signal and the previouslyrewritten 2H video signal signal are read simultaneously. As a result,the monitor display is increased by 2H as shown in FIG. 26F, so that theline sequence display is accomplished.

After the last 2H video signal (260th through 262nd) is rewritten, onescene is completed as shown in FIG. 26F. After that, the same videosignal is used to be monitored. The line sequence display is done onlyfor the initial two seconds, and the scene sequence display is donelater (see FIG. 24). Thus, the inserted scene can be monitored insubstantial synchronism with the audio signal.

When a plurality of scenes are inserted, the first scene of everydifferent scene or picture is displayed in the line sequence manner. Ifthe mode code of the identification code includes information whetherthe inserted scene is the same or different, the scene condition can bedetermined easily. Moreover, the determination output controls thememory mode of the memory means 60.

It will be obvious to those having ordinary skill in the art that manychanges may be made in the above described details of the preferredembodiments of the present invention without departing from the spiritand scope of the present invention. For example, the postrecordingprocess is only for postrecording the audio signal in the discussedembodiment, however, the video signal may be postrecorded, or a desiredone of the audio and video signals may be postrecorded. The embodimentswere discussed in the condition that T=16, N=10 and M=6, however, thevalues N and M are not limited to these values. Therefore, the scope ofthe present invention should be determined only by the following claims.

What is claimed is:
 1. A method of recording a digital audio signal anda digital video signal, comprising the steps of:forming a compositedigital signal having bits 1 . . . (N+M) (N,M: positive integers) from adigital audio signal component having bits 1 . . . N, where bit 1 is theLSB and bit N is the MSB, and a digital video signal component havingbits 1 . . . M, where bit 1 is the LSB and bit M is the MSB, whereinbits 1 . . . M of the composite digital signal are bits M . . . 1respectively of the digital video signal component and bits (M+1) . . .(M+N) of the composite digital signal are bits 1 . . . N respectively ofthe digital audio signal component; and recording the composite digitalsignal in a recording medium.
 2. The method according to claim 1,wherein the composite digital signal is recorded on a magnetic tape by arotary magnetic head.
 3. The method according to claim 1 furthercomprising inverting the kth bit (k: a positive integer no greater thanM) of the digital video signal component prior to said forming step. 4.A recording apparatus for a digital audio signal and a digital videosignal, comprising:mixing means for receiving a digital audio signalcomponent having bits 1 . . . N, where bit 1 is the LSB and bit N is theMSB, and a digital video signal component having bits 1 . . . M, wherebit 1 is the LSB and bit M is the MSB (N,M: positive integers) andforming a composite digital signal having bits 1 . . . (N+M) by mixingthe digital audio signal component and the digital video signalcomponent, wherein bits 1 . . . M of the composite digital signal arebits M . . . 1 respectively of the digital video signal component andbits (M+1) . . . (M+N) of the composite digital signal are bits 1 . . .N respectively of the digital audio signal component; and recordingmeans for recording the composite digital signal from said mixing meanson a recording medium.
 5. A recording apparatus according to claim 4,wherein said recording means includes a rotary magnetic head so as torecord the composite digital signal on a magnetic tape.
 6. A recordingapparatus according to claim 4 further comprising bit inverting meansfor inverting the kth bit (k: a positive integer no greater than M) ofthe digital video signal component prior to said mixing means receivingthe digital video signal component.
 7. A recording apparatus accordingto claim 4, comprising:a first analog-to-digital converter forconverting an analog audio signal into the digital audio signalcomponent in response to a first sampling clock; a secondanalog-to-digital converter for converting an analog video signal intothe digital video signal component in response to a second samplingclock; and timing conversion means for converting timing of the digitalvideo signal component from said second analog-to-digital converter suchthat the timing conversion means provides a digital video signalcomponent that is synchronized with the first sampling clock; andwherein the mixing means receive the digital audio signal component fromthe first analog-to-digital converter and the digital video signalcomponent from said timing conversion means.
 8. A reproducing apparatusfor a digital audio signal and a digital video signal,comprising:reproducing means for reproducing a composite digital signalhaving bits 1 . . . (N+M) (N,M: positive integers) from a recordingmedium; and separation means for separating the composite digital signalinto a digital audio signal component having bits 1 . . . N, where bit 1is the LSB and bit N is the MSB and a digital video signal componenthaving bits 1 . . . M, where bit 1 is the LSB and bit M is the MSB, saidseparation means also for reordering the bits of the digital videosignal component, where bits 1 . . . M of the composite digital signalare bits M . . . 1 respectively of the digital video signal componentand bits (M+1) . . . (M+N) of the composite digital signal are bits 1 .. . N respectively of the digital audio signal component.
 9. Areproducing apparatus according to claim 8, further comprising audiooutput means connected to receive the digital audio signal component andgenerate an acoustic signal in response thereto.
 10. A reproducingapparatus according to claim 8, further comprising video output meansconnected to receive the digital video signal component and generate avisual signal in response thereto.
 11. A reproducing apparatus accordingto claim 8, further comprising:a character generator for generating avideo signal of an image to be superimposed; and means for inserting thevideo signal from said character generator into the digital video signalcomponent from said separation means; whereby a predetermined image canbe superimposed on the image represented by the digital video signalcomponent.
 12. A reproducing apparatus according to claim 8, whereinsaid reproducing means includes a rotary magnetic head so as toreproduce the composite digital signal from a magnetic tape.
 13. Arecording and reproducing apparatus for a digital audio signal and adigital video signal, comprising:first bit inverting means for receivingan M-bit digital video input signal (M: positive integer) and providingan M-bit digital video output signal that is the same as the M-bitdigital video input signal except that the kth bit (k: a positiveinteger no greater than M) of the M-bit digital video output signal isof the opposite state from the kth bit of the M-bit digital video inputsignal; mixing means for forming an (N+M)-bit recording digital signal(N: positive integer) by mixing an N-bit digital audio signal as upperbits and the M-bit digital video output signal from said first bitinverting means as lower bits; recording means for recording said(N+M)-bit digital signal produced from said mixing means on a recordingmedium; reproducing means for reproducing said (N+M)-bit digital signalfrom said recording medium; separation means for receiving the (N+M)-bitdigital signal produced from said reproducing means and separating theN-bit digital audio signal and the M-bit digital video output signalfrom the (N+M)-bit digital signal; and second bit inverting means forreceiving the M-bit digital video output signal from the separationmeans and inverting again the kth bit to reproduce the input videosignal.
 14. A recording and reproducing apparatus according to claim 13,further comprising a display device for displaying the reproduced inputvideo signal.
 15. A method of reproducing a digital audio signal and adigital video signal, comprising the steps of:reproducing a compositedigital signal having bits 1 . . . (N+M) (N,M: positive integers) from arecording medium; and separating the composite digital signal into adigital audio signal component having bits 1 . . . N, where bit 1 is theLSB and bit N is the MSB, and a digital video signal component havingbits 1 . . . M, where bit 1 is the LSB and bit M is the MSB, saidseparating including reordering the bits of the digital video signalcomponent, where bits 1 . . . M of the composite digital signal are bitsM . . . 1 respectively of the digital video signal component and bits(M+1) . . . (M+N) of the composite digital signal are bits 1 . . . Nrespectively of the digital audio signal component.
 16. The methodaccording to claim 15, further comprising displaying the digital videosignal component on a display device after said separating step.
 17. Themethod according to claim 15, further comprising supplying the digitalaudio signal component to an audio output means to generate an acousticsignal.
 18. The method according to claim 15, wherein the compositedigital signal is reproduced from a magnetic tape by a rotary magnetichead.
 19. A method of recording and reproducing a digital audio signaland a digital video signal, comprising the steps of:(a) receiving adigital audio signal component having bits 1 . . . N, where bit 1 is theLSB and bit N is the MSB (N: positive integer) from a digital audiosignal source, (b) receiving a digital video signal component havingbits 1 . . . M, where bit 1 is the LSB and bit M is the MSB (M: positiveinteger) from a digital video signal source, (c) forming a compositedigital signal having bits 1 . . . (N+M), wherein bits 1 . . . M of thecomposite digital signals are bits M . . . 1 respectively of the digitalvideo signal component and bits (M+1) . . . (M+N) of the compositedigital signal are bits 1 . . . N respectively of the digital audiosignal component, (d) recording the composite digital signal in arecording medium, (e) subsequently reproducing the composite digitalsignal from the recording medium, (f) separating the digital audiosignal component and the digital video signal component from thecomposite digital signal reproduced from the recording medium, and (g)employing the digital audio signal component to generate an audiblesound and the digital video signal component to generate a visibleimage.
 20. A method of recording and reproducing a digital audio signaland a digital video signal, comprising the steps of:(a) receiving anN-bit digital audio signal component (N: positive integer) from adigital audio signal source, (b) receiving an M-bit digital video inputsignal component (M: positive integer) from a digital video signalsource, (c) inverting the kth bit (k: a positive integer no greater thanM) of the digital video input signal component to form an M-bit digitalvideo output signal component, (d) forming a composite digital signalfrom the digital audio signal component and the digital video outputsignal component, (e) recording the composite digital signal in arecording medium, (f) subsequently reproducing the composite digitalsignal from the recording medium, (g) separating the digital audiosignal component and the digital video output signal component from thecomposite digital signal reproduced from the recording medium, (h)inverting the kth bit of the digital video output signal component toproduce an output digital video signal, and (i) employing the digitalaudio signal component to generate an audible sound and the outputdigital video signal to generate a visible image.